1. Field Of The Invention
The present invention relates to a liquid crystal display panel, and more specifically to a compensating capacitor provided for each pixel in an active matrix liquid crystal display panel.
2. Description Of Related Art
Liquid crystal devices are energetically researched and developed as display apparatuses and light modulation devices. In general, the liquid crystal device is fundamentally formed of a pair of electrode plates opposing to each other, and a liquid crystal material sandwiched between the pair of electrode plates. In a liquid crystal device including a plurality of pixels, the electrodes formed on one of the pair of electrode plates are, in many cases, different in size from those formed on the other electrode plate. Particularly, in an active matrix liquid crystal display panel including switching devices such as a thin film transistor (TFT), the switching devices and pixel electrodes connected thereto are formed on one of the pair of electrode plates (main plate), and a common opposing electrode is formed on the whole of the other electrode plate (opposing plate).
The active matrix liquid crystal display panel including switching thin film transistors is widely used at present, since it is very advantageous in that it can be realized in a very thin structure and can be driven with a lower consumed electric power. However, the active matrix liquid crystal display panel has a problem in which variation or deviation in alignment between a gate electrode and a source electrode in the thin film transistor results in variation of an inevitable parasitic capacitance formed between the gate electrode and the source electrode, with the result that the voltage on a pixel electrode connected to the source electrode changes from one pixel to another, so that unevenness occurs in contrast, and therefore, picture quality deteriorates.
In order to overcome this problem, Japanese Patent Application Laid-open Publication JP-A-02-079476 has proposed one method, in which, as shown in FIG. 1, a gate electrode 3 is deposited on a glass substrate 1, and a semiconductor thin film 6 is formed through an insulting film 5 on the gate electrode 3, and further, a drain electrode 8 is formed on a center region of the semiconductor thin film 6, and a pair of source electrodes 9 are formed on opposite end regions of the semiconductor thin film 6, so that a pair of thin film transistors are constructed in symmetry to each other. The pair of thin film transistors are connected to each other in parallel.
With this arrangement, if variation or deviation in alignment in a manufacturing process results in increase of a gate-source capacitance in one of the pair of thin film transistors, the gate-source capacitance decreases in the other of the pair of thin film transistors. Accordingly, variation or fluctuation of the total gate-source capacitance in the pair of parallel connected thin film transistors is prevented or compensated.
Japanese Patent Application Laid-open Publication JP-A-04-068319 has proposed another method as diagrammatically shown in FIG. 2, in which elements corresponding in function to those shown in FIG. 1 are given the same reference numerals. As shown in FIG. 2, in proximity of an intersection between a gate bus line 2 and a drain bus line 7, a gate electrode 3 extends from the gate bus line 2, and a semiconductor thin film 6 is formed through a not-shown insulating film on the gate electrode 3. A drain electrode 8 branches out of the drain bus line 7 so as to extend over one end portion of the semiconductor thin film 6, and a source electrode 9 is formed at the opposite end portion of the semiconductor thin film 6, and is connected to a pixel electrode 11. Thus, a thin film transistor is formed. Furthermore, a compensation capacitor electrode 10 extends from the source electrode 9 so as to take a long way around an extension of the gate electrode 3 and to partially overlie the extension of the gate electrode 3 at the side opposite to the source electrode 9. With this arrangement, variation of the gate-source capacitance, which might be caused by variation or deviation in alignment between the gate electrode 3 and the source electrode 9 in a manufacturing process, can be prevented or compensated.
In the above mentioned conventional methods, however, by additional or compensating electrodes provided for the intention of uniformizing the gate-source capacitance of all the thin film transistors, the overall size of the liquid crystal display panel is inevitably increased or the aperture ratio of each pixel is inevitably lowered. For example, in the case of a liquid crystal display panel having a pixel pitch on the order of 300 .mu.m, the pixel aperture ratio is lowered 10% to 20% by the conventional methods for uniformizing the inevitable gate-source capacitance of the thin film transistors.